1. The Field of the Invention
The present invention relates to forming an isolation trench in a semiconductor device. In particular, the present invention relates to a method of forming an isolation trench in an etching process for a semiconductor device that combines a spacer etch with a trench etch.
2. The Relevant Technology
An isolation trench is used in an active area associated with a microelectronic device on a semiconductor substrate or on a substrate assembly. Isolation trenches allow microelectronics devices to be placed increasingly closer to each other without causing detrimental electronic interaction such as unwanted capacitance build-up and cross-talk. In the context of this document, the term semiconductive substrate is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above. The term substrate assembly is intended herein to mean a substrate having one or more layers or structures formed thereon. As such, the substrate assembly may be, by way of example and not by way of limitation, a doped silicon semiconductor substrate typical of a semiconductor wafer.
The ever-present pressure upon the microelectronics industry to shrink electronic devices and to crowd a higher number of electronic devices onto a single die, called miniaturization, has required the use of such structures as isolation trenches.
In the prior state of the art, an etching process of fill material within an isolation trench has been problematic. As seen in FIG. 1, a semiconductor substrate 12 has an isolation trench substantially filled up with an isolation material 48. A pad oxide 14 is situated on the active area of semiconductor substrate 12. Isolation material 48 exhibits a non-planarity at the top surface thereof between corners 62, particularly as is seen at reference numeral 46 in FIG. 1. The non-planarity of the top surface of isolation material 48 is due to dissimilarity of etch rates between isolation material 48 and pad oxide 14, particularly at corners 62 of the active area of semiconductor substrate 12.
An active area may be formed within semiconductor substrate 12 immediately beneath pad 14, and adjacent isolation material 48. A problem that is inherent in such non-planarity of fill material within an isolation trench is that corners 62 may leave the active area of semiconductor substrate 12 exposed. As such, isolation material 48 will not prevent layers formed thereon from contacting the active area of semiconductor substrate 12 at corners 62. Contact of this sort is detrimental in that it causes charge and current leakage. Isolation material 48 is also unable to prevent unwanted thermal oxide encroachment through corners 62 into the active area of semiconductor substrate 12.
What is needed is a method of forming an isolation trench, where subsequent etching of fill material within the isolation trench of such method prevents overlying layers from having contact with an adjacent active area, and prevents unwanted thermal oxide encroachment into the active area. What is also needed is a method of forming an isolation trench wherein etching or planarizing such as by chemical mechanical planarization (CMP) of isolation trench materials is accomplished without forming a recess at the intersection of the fill material in the isolation trench and the material of the active area within the semiconductor substrate.